(1) Field of the Invention
The present invention relates to a structure of a solid-state image sensing device in which signal charges generated by a plurality of photo receiving elements arranged in a matrix form are transferred in a vertical direction by means of a plurality of vertical registers and the signal charges transferred by means of the plurality of vertical registers are partially transferred by means of a plurality of horizontal registers.
(2) Background of the Art
It becomes necessary to provide a high resolution for solid-state image sensing devices commonly used as photographing means in video cameras in order to meet requirements for highly resolved video cameras. Specifically, the number of pixels (constituted by the photo receiving elements) arranged in a matrix form must be increased. Although the number of pixels in the solid-state image sensing device of a commercially available video camera are about 300 thousand through 400 thousand about 2,000,000 pixels are required in the case of the video camera applicable to an HDTV (High Definition Television) since the resolution is five times higher than that in the comercially available video camera.
In addition, since an increase in the size of a chip in proportion to the increase in the number of pixels is not allowed, the number of pixels must be remarkably increased with no increase in the chip size.
Since a limit of the number of pixels aligned in a horizontal direction is generally determined according to a unit length of one bit of a horizontal register with the chip size of the solid-state image sensing device constant, this horizontal register provides a factor for restricting the high resolution of the image sensing device.
A Japanese Patent Application Second Publication (Examined) No. Heisei 1-13676 published on Mar. 7, 1989 exemplifies the structure of the solid-state image sensing device in which a plurality of horizontal registers are arranged in parallel to one another and signal charges generated by means of the photo receiving elements and transferred in the vertical direction by means of the vertical registers are shared and distributed into a plurality of horizontal registers so that an improvement in integrations of the pixels in the horizontal direction can be achieved.
A result of study on the solid-state image sensing devices in which the horizontal registers are installed is published in the paper of Television Society Vol. 41, No. 11 (published in 1987) titled as "Super High Resolution CCD Image Sensor" of pages 74 to 80.
One previously proposed solid-state image sensing device includes: a photo receiving portion in which photo receiving elements are arranged in the matrix form; a storage portion located below the photo receiving portion; a gate region located at a side of the storage portion opposite to the photo receiving portion, the gate region transferring signal charges to a first horizontal register at the same time when receiving a gate voltage.
The first horizontal register is arranged at a side of the gate region opposite the storage portion. A control gate is arranged at a side of the first horizontal register opposite the gate region. A second horizontal register is arraged at a side of the control gate opposite the first horizontal register. A multiplexor is provided for multiplexing the signal charges derived from the first and second horizontal registers.
The control gate transfers signal charges transferred from any other vertical registers which do not correspond to respective channel stoppers provided at every other interval along the control gate to the second horizontal register.
In addition, the control gate is formed by a first layer of a polycrystalline silicon layer. The polycrystalline silicon layer is located above an insulating film formed on a main surface of a semiconductor substrate.
It is noted that an interlayer insulating film encloses the control gate and the transfer electrodes are formed so as to intersect the control gate via the interlayer insulating film. The transfer electrodes serve to drive the horizontal registers. The transfer electrodes for the horizontal registers are arranged so that the second and third polycrystalline silicon layers are alternately arranged in the horizontal direction. One of the transfer electrodes constituted by one of the polycrystalline silicon layers receives a pulse .phi..sub.1 and the other transfer electrode constituted by the other polycrystalline silicon layer receives a pulse .phi..sub.2.
Since the previously proposed solid-state image sensing device applicable to an HDVS is provided with the control gate having a relatively long length of, e.g., about 15 mm, an application of a gate voltage .phi..sub.HP to the control gate is carried out from both ends of the control gate in order to reduce the propagation delay time of the control signal transmitted thereto to as small as possible.
However, since a specific resistance (resistivity) of the polycrystalline silicon layer is never low and therefore an equivalent circuit of a transmission path of the gate voltage is constituted by a plurality of R-C circuits, a waveform of the gate voltage .phi..sub.HP is distorted at the control gate and/or its amplitude becomes reduced. In this way, when a time constant of the transmission path becomes large, the propagation delay occurs and gives an ill effect on the operating characteristics of the control gate.
Especially, since the transfer of the signal charges toward the horizontal registers by means of the control gate must be carried out within a very short horizontal blanking interval in a television system of HDVS (High Definition Video System), such a propagation delay as described above cannot be neglected any more.